Conventional contact trench formation by way of reactive-ion etching (RIE) results in a device with poor quality. In particular, plasma damage and polymer residue in the bottom of the contact trench occur with RIE. Further, with a poly-open chemical-mechanical planarization (CMP) process, undesirable trace amounts of silicon nitride (SiN) result in contact trenches with poor quality.
The Fermi-level pinning effect is significant in many commercially important semiconductors (Silicon (Si), Germanium (Ge), and Gallium Arsenide (GaAs)), and can make the design of semiconductor devices difficult. However, Fermi-level pinning serves as an inherent benefit for Ge source/drain contacts. By using Fermi-level pinning the Schottky barrier height (SBH) lowering/optimization, contact resistance can be reduced.
A need therefore exists for methodology enabling Fermi-level pinning for both source/drain contacts, in particular, a boron doped Ge (Ge:B) trench contact for a source/drain in a PFET region and a Group III-V trench contact for a source/drain in a NFET region and the resulting device. It is critical to minimize SBH between metal Fermi-level to conduction band of semiconductor using Ge:B for PFET and to valence band of semiconductor using Group III-V for NFET.